The big idea: The fetch–decode–execute cycle has stages, and each uses different parts of the processor.
Pipelining overlaps them: while one instruction is executing, the next is being decoded and a third is being fetched. No stage sits idle waiting for the others.
The stages pipelining overlaps — fetch, decode, execute, each using different parts of the processor.
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| Without pipelining | With a 3-stage pipeline | |
|---|---|---|
| Stages busy at once | One | Three |
| 3 instructions take | 9 stage-times | 5 stage-times |
| 100 instructions take | 300 | 102 |
| One instruction still takes | 3 stage-times | 3 — unchanged |
| What improves | Nothing | Throughput, not latency |
Throughput, not latency: Pipelining does not make any single instruction finish sooner — it still passes through every stage.
What improves is how many complete per second. This distinction is the most reliably examined point in the topic.
The laundry analogy, precisely: Washing, drying and folding one load takes the same time however you organise it. But you can dry load 1 while washing load 2.
The machines are the stages; one load is one instruction; four loads finish far sooner even though each still takes as long.
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Branches
- An if means the next instruction is not yet known
- The pipeline has already fetched the wrong ones
- They must be discarded and the pipeline refilled
- This is the expensive one
Data dependency
- An instruction needs the result of the one before it
- It must wait until that result exists
- The pipeline holds a bubble while it does
Resource conflict
- Two stages want the same hardware at once
- One waits — the other proceeds
- Eased by duplicating the contended unit
Branch prediction, and why it is a guess: Processors guess which way a branch will go and fetch accordingly. Guess right and nothing is lost; guess wrong and the pipeline must be flushed and refilled.
A deeper pipeline overlaps more — but a wrong guess then costs more, because there is more to throw away.
How this is tested — you must compute the saving and be precise that throughput improves while latency does not. It comes up two ways:
Paper 1 Section A
- Describe the process of pipelining, 3-4 marks
- Calculate how long n instructions take
- State one cause of a stall
Paper 1 Section B — case study
- Explain why a branch is expensive
- Explain why one instruction is no faster
The classic trap: Saying pipelining "makes instructions faster". Each instruction takes exactly as long. More of them complete per second — that is throughput, not latency.
A processor has a 4-stage pipeline, each stage taking 1 ns. Determine how long 50 instructions take with and without pipelining, and explain why the saving is not 4×.
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