The big idea: A CPU does one thing, over and over, billions of times a second:
Fetch the next instruction · decode what it means · execute it.
Then it starts again. That loop is the whole job.
Fetch
Collect the next instruction from memory and bring it into the CPU.
Uses the PC, MAR, MDR and IR
Decode
The control unit works out what the instruction is asking for.
Uses the CU and the IR
Execute
The instruction is carried out — usually a calculation in the ALU.
Uses the ALU and the accumulator
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Our instruction again: ADD 5, in memory box 20. Step through and watch which register fills at each stage — the destination of each move is highlighted.
Six moves make one instruction. Registers fill in order, then the ALU produces the answer.
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The step people get wrong: The PC increases during fetch, not at the end.
That matters: a jump instruction works by overwriting the PC during execute. If the PC were bumped afterwards, it would undo the jump.
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Every fetch is a trip to memory: Fetching uses all three buses at once: the address goes out, a read signal goes out, and the instruction comes back on the data bus.
The same trip the fetch stage makes, bus by bus.
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Registers and buses together: MAR → address bus. The address the CPU wants goes out from here.
Data bus → MDR. Whatever comes back arrives here first, then moves to the IR.
How this is tested — the marks are in the ORDER and the REGISTER NAMES, not the word count. It comes up two ways:
Paper 1 Section A
- Describe the cycle, 3-6 marks
- Name the registers used at each stage
- Explain when and why the PC is increased
Paper 1 Section B — case study
- Trace an instruction from the case study's program
- Explain what limits how fast that system runs
The classic trap: Describing all three stages but naming no registers caps a six-mark answer at about three. The register names are half the marks.
Describe the fetch, decode and execute cycle, naming the registers involved at each stage.
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