IB Computer Science HL — All Flashcards

It controls and coordinates the CPU: it fetches and decodes instructions and sends control signals telling the other components what to do and when. It does no calculating itself.

It performs all arithmetic operations (add, subtract, multiply, divide) and logic operations (AND, OR, NOT, and comparisons) on data.

The address of the **next** instruction to be executed. It advances after each instruction is fetched.

The MAR holds the **address** being accessed; the MDR holds the **value** travelling to or from memory. Address versus data.

The instruction currently being executed, held there while the CU decodes and carries it out.

The number the ALU is working on — both the value going in and the answer coming out. ADD 5 turns a 12 in the accumulator into 17, in the same register.

**Address bus** — the memory address (one-way, CPU → memory). **Data bus** — the data or instruction itself (two-way). **Control bus** — the CU's commands and timing signals (two-way).

Only work that can be divided between cores benefits. If each step depends on the previous result, the work cannot be split and extra cores sit idle.

Registers sit inside the CPU and can be reached almost instantly, whereas RAM is much slower. Holding working values in registers stops the ALU waiting on memory.

To perform many simple calculations at the same time. It has thousands of small cores, which suits work made of many identical independent sums — pixels, machine learning, simulations.

A CPU has a few powerful cores that handle complicated varied work in order. A GPU has thousands of simple cores that do the same calculation simultaneously.

Machine learning (multiplying huge grids of numbers) and large simulations (updating millions of independent points). Both repeat one calculation across many values.

When the work is a chain of steps that each need the previous answer. Nothing can run in parallel, and GPU cores are individually weaker than CPU cores.

The CPU runs the program, decides what needs doing, sends the repetitive part and its data to the GPU, and collects the result when it is finished. The GPU never chooses its own work.

A **CPU** has a few powerful cores optimised for **latency** on one stream. A **GPU** has thousands of simple cores optimised for **throughput** on many values at once.

Its cores run in **lockstep** on the same instruction, so a branch forces some to idle while the others proceed.

**Are the operations independent?** Can they run in any order, simultaneously, without needing each other's results?

Training is enormous **parallel matrix arithmetic** over a whole dataset. Inference is one input, one pass — small enough for a CPU or a phone.

If the work is sequential or branch-heavy it cannot parallelise, each GPU core is slower than a CPU core, and the data must be **copied there and back**.

Registers, then cache (L1, L2, L3), then RAM. Each step holds more and takes longer to reach.

To hold recently used data and instructions in a small, very fast store close to the CPU, so most requests avoid the slower trip to RAM.

A hit means the value is already in cache, so no trip to RAM is needed. A miss means it is not, so it is fetched from RAM and copied into cache for next time.

RAM is a large volatile working space holding programs in use; it empties when power is lost. ROM is small, non-volatile and read only, holding the start-up program.

Because programs tend to reuse the same values shortly afterwards, so caching it turns the next request into a hit.

Fetch the next instruction from memory, decode it in the control unit, then execute it — usually a calculation in the ALU. The cycle then repeats.

The PC holds the address, which is copied to the MAR. Memory returns the instruction into the MDR, and it moves to the IR. The PC is then increased.

During fetch. A jump instruction works by writing a new address into the PC during execute — increasing it afterwards would overwrite the jump.

The control unit reads the instruction held in the IR, works out which operation is needed, and sends control signals to the parts that will carry it out.

All three: the address bus carries the address out, the control bus carries the read signal, and the data bus brings the instruction back.

Overlapping the stages of the fetch–decode–execute cycle, so one instruction executes while the next is decoded and a third is fetched.